Cinder is looking for an ASIC/FPGA Verification Engineer (UVM) to fill a role for our client in San Jose, CA. This is a full time, 40 hour per week opportunity with a full benefits package that includes PTO!
Responsibilities include but are not limited to:
- Verifying the design and implementation of the industry's leading network monitoring devices.
- Being responsible for verification of the FPGA and / or ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies such as UVM.
- Developing and integrating current and future designs into UVM environments
- Understanding the design and implementation, defining the verification scope, developing the verification infrastructure and verifying the correctness of the design.
- Generating reports providing coverage and test results.
- Integrating verification into continuous integration flow.
- Working with architects, designers, software and hardware teams to accomplish your tasks.
- Master’s Degree in Electrical Engineering, Computer Science or Computer Engineering with at least 3+ years of relevant experience OR an Advanced Degree with equivalent experience.
- Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
- Experience with design and verification tools.
- Experience in crafting test bench environments for unit and system level verification.
- Expertise in System Verilog.
- Strong debugging, troubleshooting and analytical skills
- Technically curious and driven to learn new skills.
- Self-starter, flexible, adaptable, collaborative and motivated to champion continuous improvement.
- Perl and C/C++ programming language experience.
- Prior experience with networking and packet processing.
- Strong communication skills and ability & desire to work as a great teammate.
Job Location: Must be done onsite
Shift: Normal business hours
We are unable to provide visa sponsorship at this time.